The present invention relates generally to field programmable devices, and more particularly to a field programmable device, such as a ROM (Read Only Memory), PROM (Programmable Read Only Memory), FPLA (Field Programmable Logic Array) and the like, capable of being functionally tested before information is written in the device.
In a field programmable device such as a PROM or ROM, that is, a memory device capable of having information written into it in the field, all memory cells within the memory device, before the write-in of information, are in a "0" logic low or a "1" logic high state. Therefore, tests cannot be performed to detect whether a selected memory cell is in a normal or abnormal state.
An example of a conventional memory device of the above type comprises X and Y address inverters a X-decoder driver, a Y-decoder, a memory cell part, a multiplexer, and an output circuit. However, when all the memory cells of the memory cell part are in the same state, even upon breakdown of one or more peripheral circuits, for example, address inverters, decoder driver, or output circuit, the data read-out of the memory cells is all the same. Accordingly, it is impossible to know whether the cells are in normal or abnormal states. Even assuming that there are abnormalities, it is not possible to know where the abnormalities exist.
Hence, a system was devised in which a row of extra test bits and a test word are provided within the memory cell part. In this system, by storing predetermined code patterns, for example "1,0,1,0, . . . ", into the test bit row and test word, the peripheral circuits can be tested by reading these code patterns. But, since there are many items within the memory device to be tested, the above system is insufficient because it can only perform some of the required tests. Therefore, more than simply providing a test bit row and a test word within the memory cell part, and writing a code patterns such as "1,0,1,0, . . . ", is required an inventive code pattern must be devised. But, even the inventive code pattern is insufficient for performing the necessary tests since it sometimes cannot detect short-circuits in the wiring.
In view of the above problems, the applicants have proposed a field programmable device in the U.S. Pat. No. 4,312,067 issued to Shurasaka entitled "A FIELD PROGRAMMABLE DEVICE", filed on Nov. 19, 1979, which can be subjected to various tests, and accordingly capable of being tested before shipment. However, it has been discovered that this system is incapable of completely testing the operational speed of the memory device. This is because the capacitance of a memory cell in the field programmable device is different before information is written into the device than after information is written into the device. Accordingly, the word line capacitance varies with respect to the write-in ratio.
The time to read data out of the device, and the word line rise time vary in accordance with the above capacitance. These changes are not considerable, but since field programmable devices, especially the high-speed devices such as a Schottky-type PROM have a fast average access time of 20 nses in the 4-kilobit devices, even the slightest change becomes a problem.
The word line capacity is affected by the manufacturing process, and thus computation of the word line capacity is difficult, and is preferably obtained by actual measurements.
In the applicants' above-mentioned previously proposed field programmable device, the write-in ratio of both the test bit row and of the test word is 50%, hence capable of being subjected to a speed check of a 50% write-in ratio, but incapable of performing speed checks in the remaining parts. Therefore, when the user performs a 100% write-in (this is done quite often), the access time can become much higher than that of the nominal value.